Alessandro Palla

Alessandro Palla

Senior Deep Learning Engineer

Intel Corporation


Hi. My name is Alessandro Palla and I’m a Senior Deep Learning Engineer @ Intel.

I have worked both in industry (Intel, Dialog Semiconductor, STMicroelectronics) and in academia as a researcher, on various projects, from HW VHDL/Verilog design to C/C++ firmware and system level design and verification and Machine Learning.

In my working experience, I have acquired many communication skills that make me proficient in the interaction with people with different nationalities in a multicultural environment.

Welcome to my website!


  • Artificial Intelligence
  • Hardware Design
  • Assistive Technology


  • PhD in Embedded System Design, 2018

    University of Pisa

  • MSc in Electronic Engineering, 2014

    University of Pisa

  • BSc in Electronic Engineering, 2012

    University of Pisa



Jupyter, Numpy, Networkx, Scipy, Flask, Tensorflow, Keras, PyTorch

Machine Learning

Tensorflow, Keras, PyTorch, Caffe


Embedded C/C++, VHDL and Verilog, PCB design, Electronic lab equimpements


Bash, Unix, Git, SVN, Docker, Kubernetes

Math & Algorithms

DSP, Statistics, Optimization, Regression

Social Skills

Project Management, Technical ownership



Senior Deep Learning Engineer

Intel Corporation

Jul 2017 – Present Pisa, Italy/ Dublin, Ireland/ Seattle, USA

Main duties:

  • Architectural system design for next Intel hw CNN IP for machine learning
  • Neural Network optimization and hardware scheduling in leading edge Intel embedded chips.
  • Architectural design and validation of embedded always-on ultra low-power real time face recognition and keyword spotting hardware IPs


  • Techinal owner of NN compiler optimization techniques architecture
  • Techinal integration of Intel acquired company Vertex AI


  • Automatic scene reconstruction using 3D autoencoder CNN
  • Tailored Neural Architecture Search for Intel AI accelerator

Application Engineer


Apr 2014 – Nov 2014 Agrate Brianza, Italy

Design and implementation of a human-machine interface based on microphone array.

  • Design, implementation and validation of speech enhancement algorithms (Beamforming, Voice Activity Detection, Noise Canceling) in a Cortex M4F based micro-controller.
  • Design and implementation of a human-machine interface based on microphone array for people with motor skill impairment using the aforementioned framework.

Application Engineer

Dialog Semiconductor

Jul 2013 – Sep 2013 Swindon, UK

Power Management IC (PMIC) validation

  • Design of a new methodology for PMIC efficiency measurement using current pulse with low duty cycle to avoid chip heating and efficiency loss.
  • Temperature characterization and visualization during IC power cycles

Recent Publications

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